Simulation power domain ESD protective circuit



The present invention relates to the integrated circuit electro-static discharge protection design technology field, discloses a simulation power domain ESD (Electro-Static Discharge) protective circuit, is applied to the ESD circuit design of a multi-power domain digital-analog hybrid chip, and is especially suitable for the ESD circuit design of the simulation power domain. Through adoption of the jump source domain triggering technology to realize the ESD protection of the simulation power domain core circuit, satisfy low power consumption and anti-noise requirements of the chip and solve the problem of the false triggering of an ESD discharge circuit when the normal work of the chip.
本发明涉及微电子学中的集成电路(IC:Integrated Circuit)静电放电(ESD:Electro‑Static Discharge)保护设计技术领域,公开了一种模拟电源域ESD保护电路,应用于多电源域数模混合芯片的ESD电路设计,尤其适用于模拟电源域的ESD电路设计,通过跨电源域触发技术,即实现了对模拟电源域内核电路的ESD保护,也满足芯片的低功耗、抗噪声的要求,同时解决芯片正常工作时ESD放电电路误触发的问题。




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